Portable industrial and consumer products tend toward smaller size, lower cost and increased functionality. These requirements place greater emphasis on the development of semiconductor packaging technologies which can accommodate larger, more complex integrated circuits in thinner packages.
Conventional surface mount technology utilizes leaded plastic packages. However, as the pitch and size of the leaded plastic packages keep on being reduced, such problems as poor solder assembly yields, due to poor control of lead coplanarity, and poor fine pitch solder printing yields, due to continuing shrinking of the lead pitch, continue to remain of major importance.
One type of packaging which seemed to overcome these problems is an Overmolded Plastic Pad Array Carrier (OMPAC) technology. OMPAC assembly utilizes a double-sided printed circuit or wiring board laminate. (Hereinafter the printed circuit board or printed wiring board will be referred to as "PWB"). The top side metallization of the PWB is comprised of a die pad for die attachment of an integrated circuit (IC) unit and grounding and wirebond fingers. The IC unit may include a semiconductor chip (a die), or multiple semiconductor chips, or a Multi-Chip Module (MCM) tile including one or more chips and/or some other elements of the device on a commonly shared silicon substrate. The wirebond fingers extend outward to plated through holes (hereinafter referred to as "thruholes") in the PWB located near the edge of the package. The thruholes provide an electrical continuity from the top side to the bottom side of the PWB. The signal path is completed on the bottom side of the PWB by plated copper traces extending from the thruholes to solder pads for solder bump termination. Except for the solder bumps, all metal features on the PWB are typically photodefined, etched and electroplated with copper, nickel and gold. Conventional epoxy die attach and wire bonding technologies are used to interconnect the integrated circuit unit to the PWB. After the die and wire bonding, the PWB is overmolded using conventional epoxy transfer technology. After post-mold curing, the packages are solder bumped and electrically tested. Subsequently these are referred to as "ball grid array" (BGA) packages. Solder bumps are used for further interconnection of the BGA package, for example, to a "mother board". The mother board typically has a much larger area than the OMPAC BGA package, upon which may be arranged a number of other interconnected lumped electrical elements, such as capacitors, transformers, and resistors, which cannot be conveniently integrated into the chips or modules, as well as other packaged IC's, BGAs, plugs and connectors.
The major advantages of OMPAC BGA packages as compared to leaded surface mount packages include increased packaging interconnect density due to an evenly spaced matrix of solder connections on the bottom side of the package, higher solder assembly yields, and no lead coplanarity problems.
In FIG. 11 of the drawings is shown a schematic representation in cross-section of a representative prior art OMPAC BGA, 110, with an IC unit, 111, being a single die or chip component. Device 110 includes a PWB, 112, provided with wirebond fingers, 113, a polymer coating which acts as a solder mask, 114, on the fingers, thruholes, 115, contact pads, 116, wires, 117, interconnecting the die to wirebond fingers 113, and a molding compound, 118, enclosing the die, the wires and those portions of wirebond fingers 113 which are bonded to the wires. Contact pads 116 are further provided with solder bumps, 119, for interconnection to a mother board (not shown).
In FIG. 12 of the drawings is shown a schematic representation of another prior art device, 120, a variant of the OMPAC BGA. Here the IC unit is a silicon-on-silicon MultiChip Module (MCM) tile, 121, including a plurality of chips or dies, 122 and 123, flip-chip mounted by means of solder or conductive adhesive reflow technology to interconnection circuitry (not shown) on a silicon interconnection substrate, 124. Silicon substrate 124 is mounted on a PWB, 125, which is provided with wirebond fingers, 126, a solder mask, 127, plated thruholes, 128, and contact pads, 129. The silicon substrate is interconnected by means of wires, 130, to wirebond fingers 126. A protective shell, 131, filled with highly compliant encapsuling material, such as silicone gel, 132, protects the MCM tile and the wirebonds. Contact pads 129 are provided with solder bumps, 133, for interconnection to a mother board (not shown).
In contrast to device 110, device 120 shown in FIG. 12 avoids the molding step, thus avoiding exposure of the assembly to rigors of the molding process. However, device 120 continues the use of wirebond interconnections between the IC unit and the wirebond fingers. Wire bonding is a time-consuming procedure, which becomes more time-consuming as the number of I/O counts per die or MCM tile keeps on increasing. Also, in order to provide viable interconnections, the wirebond fingers on the PWB are gold-over-nickel plated copper. By eliminating the wirebond interconnection, the need for expensive gold-over-nickel plating of copper on the PWB would be eliminated. This would lead to a significant cost reduction. Thus, it is desirable to produce a device without wirebond interconnections. Furthermore, it is desirable to reduce the thickness of the packages.